Hi Everyone,
just a quick question.
I have created a FIFO using CoreGen and in this part there are various clocks for read and write, i want to clock the write clock at ~ 75MHz, when you look in the vhdl file that is produced, it says in the "configuration specification" that the wr_clk = 100. Do i have to change this value, i dont think i do but wondered what you think?
Are you talking about Xilinx Coregen? If not, please ignore the response.
I am not sure if frequency can be specified anywhere. When I used it, I did not specify the frequency. You need not bother to change the value if it has come.
If you are generating yours FIFO using Xilinx core gen only you can define the input /output data width, enable signals,and depth. so it does not matter whatever frequency you have choosen in your design and depth will take care of yours writting and reading frequency.