[QUETION] constrain for function mode and scan mode

[cnspy]

There's a clock in rtl like this.

sys_clk = scan_enable ? clk : ~clk;

How to constrain this and optimize it in both function mode and scan mode.

Is it will cause any problem?

What should I pay attention on it?

 

[yln2k2]

Hi ,

It is depends on what is your scan freq ? if you meet functional you will meet scan .
But you have some hold issues which can be fixed applying scan SDC and don't touch on functional part and give a run to touch SI pins only ...

If you ICC compiler you can give multiple SDC , then this problems won't be there .


regards
yln