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questions in sigma-delta ADC

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chuzi

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hi,all
i am a beginer in analog ic design and recently in my first project sigma-delta ADC.
my case is: 1 bit, cascade 2-1-1modulator, 64 OSR, in simulink SNR could be 108dB, considering KTC noise/clock jitter/nonideal opamp,SNR could be 97dB, noise level is about -140dB.
then i begin my circuit.
when simulate circuit, it is said noise floor is about -100dB, SNR lower than 80dB, why noise floor is so great? what reason may make this happen?
thanks a lot, bow to all:|

my opamp(5.6pf load):unitfreq 372Mhz,phasemargin 71.6, gain 97dB,slew rate 280V/us, input noise 5nV/sqr(hz).
in simulation, sample rate is 20MHz, input signal i choose 100khz sin-wave.
simulation software:hspice,VCS(nanosim).
thanks:)
 

sunking

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1. the sample clock?
2. the simulate software?
 

chuzi

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sorry, in simulation sample rate is 20Mhz, signal i choose 100khz,
simulation software is hspice, and VCS(nanosim)
thanks:)
 

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