questions about VCO with regulator

[gargoyle]

hello all:
i am designing a vco, the structure is regulator(bandgap+op), V-I converter and
CCO, but i found that even with noiseless power supply, the jitter of the vco is
much more worse than design the vco without regulator(only v-i converter and
cco). i am really confused.

wo should i think about the phenomena.

thanks

gargoyle

 

[simonkuo]

Do you ever checked the regulator stability?
How many stage does your OP have?

 

[gargoyle]

yes，two stage,folder cascode OP,PM=60 .

the voltage for the internal supply is stable.

i found the reason, i check and measure the waveform by using SPICE EXPLORE,(simulator:hspice). and when i change the step of TRAN analysis, the
measure differs, and stable when tran step=0.05ns, (vco output freq about 1ghz )

it is really strange

 

[gargoyle]

does some one know how to configue the .OPTION command when
simulate oscillators?

thanks

 

[jswei303]

have you checked your regulator's current supplied?
if the regulator cannot support enough current, it might cause the VDD noisy and this might be the reason I guess.