Questions about the noise fllor of the 2nd delta-sigma modulator

[davison7]

Hi~~Everybody,

Recently, I have designed a second-order Sigma-delta modulator using the CIFB architecture.

The fin = 1KHz, fs = 1MHz, and Vin = 1V.

In the first, I use the Matlab to simulate its function. The output spectrum shows that the noise floor at dc frequency is about -120dB.


But when I use the actual devices of the OPA, the Switch, and the clock generator into the Spectre for simulation, the low-frequency noise floor

rises at -90dB. It results in a worse SNR!

Could eveyone tells me that what reasons cause the low-frequency noise floor becomes worse and how to improve this problem?

Thank you very much

 

[b_ganjar]

transistor's flicker noise!

 

[yuvan]

Hi Davison,

There could be multiple reasons for it. First of all let us know if this is CTDSM or DTDSM. Second what's ur DC gain & UGB of ur First int? Do you use Dithering or something else for DAC? or this could be because of some dynamic error too. Give us more insight into ur design so as to help u