Questions about SystemC syntax/support

[bigyellow]

questions about systemc

1. Is this syntax correct, a is a bool type variable, and b is a bit_vector type variable?
a = b.range(15,0).and_reduce();

2. Does Modelsim support the mixed-simulation with system-c and VHDL/verilog, for example, testbench is written in systemc and DUT is written in VHDL?

3. Is systemc case-sensitive?

thx

 

[vikasgupta]

Re: questions about systemc

Well

Ans to question is yes it do support mixed language simulation and the answer to 3rd question is yes systemC is case sensitive as c

 

[samuraign]

questions about systemc

(1) Is it possible to call C-function from SystemC code.
(2) Is it possible to co-simulate C-code with SystemC code.

 

[mint]

Re: questions about systemc

(1) Is it possible to call C-function from SystemC code.

Yes, SystemC is based on C++ which is based on C.

(2) Is it possible to co-simulate C-code with SystemC code.

What do you want to simulate with the C-code? SystemC has a kernel that manages concurrency to emulate hardware simulation. C codes run sequentially.

 

[samuraign]

questions about systemc

I want to simulate my RX with TX C-code(already available,don't want to re-write it in SystemC) in a SystemC testbench.

 

[samuraign]

questions about systemc

yup,
I got it.
Made my C-code as sub-module or member function.