You will have to fix them, unless your chip has some special design where you don't care about reset architecture. Consult with your logic designers/test engineers/system architects to see if there are specific areas in the chip where you can waive them. In general you have to fix all violations.
From your comment that all DRC violations are showing up on reset pins, it looks like either you missed a certain mode for optimization during P&R or it might be a P&R tool setting issue. If it is a P&R tool issue, check your auto high fanout settings and auto drc disabling settings.