questions about report_constraint -all

[irun2]

Hi all,
After PR I did the STA on the design with back-annotated info. There are not any violations of setup or hold time. But when I use report_constraint -all to see the quality, max_transition and max_capacitance violations are reported, most of them related to the reset pins.
Do those violations matter and need to be fixed? or can I waive them?

 

[matter]

You will have to fix them, unless your chip has some special design where you don't care about reset architecture. Consult with your logic designers/test engineers/system architects to see if there are specific areas in the chip where you can waive them. In general you have to fix all violations.

From your comment that all DRC violations are showing up on reset pins, it looks like either you missed a certain mode for optimization during P&R or it might be a P&R tool setting issue. If it is a P&R tool issue, check your auto high fanout settings and auto drc disabling settings.

 

[irun2]

You will have to fix them, unless your chip has some special design where you don't care about reset architecture. Consult with your logic designers/test engineers/system architects to see if there are specific areas in the chip where you can waive them. In general you have to fix all violations.

From your comment that all DRC violations are showing up on reset pins, it looks like either you missed a certain mode for optimization during P&R or it might be a P&R tool setting issue. If it is a P&R tool issue, check your auto high fanout settings and auto drc disabling settings.

Thanks for the explanation, matter!
The reset is is power-on-reset. Is there any setting in Encounter which will have effects on these two you mentioned?
auto high fanout settings and auto drc disabling settings
Or they just need to be written as constraints in the timing sdc file too?

---------- Post added at 00:39 ---------- Previous post was at 00:30 ----------

Besides, did you mean that in general, as long as there're vio reported, no matter what kind of them, they should be fixed, right?

 

[matter]

Unfortunately I am not familiar with cadence flow. I am only familiar with the synopsys tools. I didn't realize that this is more cadence tool specific.

The constraints for ahfs and auto drc disabling are mainly P&R type constraints. So they don't need to be in the timing sdc file. How may transition violations are we talking about ? If it is a handful, then we can directly fix them with Ecos. But if the # of vios are in 100s or 1000s range, then going back to P&R tool will be the best option. Do you see these vio in your P&R tool as well ?

For your other question, Yes - I meant that as long as any violations (of any kind) show up, they need to fixed, unless you have waivers for them.