(* ram_style=block *)
Dear all,
i have written a vhdl code for 16K Bytes Ram for Spartan 3e , Xc3s250e , which has 250K gates ,
in after implementing design , in design summary , it says :
total equivalent gates for design is 524,379 ,
but it doesn't give any error report that it doesn't fit in the FPGA , shouldn't it give error ?
or i am wrong ? and "total equivalent gates" has another meaning , if yes , what ?
and also it says :
number of block ram : 8 from 12 , what is block ram ?
and my code is here :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ram is
port ( clk : in std_logic ;
we : in std_logic ;
a : in std_logic_vector ( 13 downto 0 ) ;
di : in std_logic_vector ( 7 downto 0 ) ;
do : out std_logic_vector ( 7 downto 0 ));
end ram;
architecture Behavioral of ram is
type ram_type is array ( 16383 downto 0 ) of std_logic_vector ( 7 downto 0 );
signal ram : ram_type ;
begin
process ( clk )
begin
if ( clk'event and clk = '1' ) then
if ( we = '1' ) then
ram ( conv_integer (a) ) <= di ;
do <= ( others =>'Z');
else
do <= ram( conv_integer (a) );
end if;
end if;
end process;
end Behavioral;
I'll be thankful you help me ...
Thanks & Regards ...