questions about ISE software and FPGA

[hm_fa_da]

(* ram_style=block *)

Dear all,

i have written a vhdl code for 16K Bytes Ram for Spartan 3e , Xc3s250e , which has 250K gates ,
in after implementing design , in design summary , it says :
total equivalent gates for design is 524,379 ,
but it doesn't give any error report that it doesn't fit in the FPGA , shouldn't it give error ?
or i am wrong ? and "total equivalent gates" has another meaning , if yes , what ?
and also it says :
number of block ram : 8 from 12 , what is block ram ?

and my code is here :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ram is
port ( clk : in std_logic ;
we : in std_logic ;
a : in std_logic_vector ( 13 downto 0 ) ;
di : in std_logic_vector ( 7 downto 0 ) ;
do : out std_logic_vector ( 7 downto 0 ));

end ram;

architecture Behavioral of ram is
type ram_type is array ( 16383 downto 0 ) of std_logic_vector ( 7 downto 0 );
signal ram : ram_type ;
begin
process ( clk )
begin
if ( clk'event and clk = '1' ) then
if ( we = '1' ) then
ram ( conv_integer (a) ) <= di ;
do <= ( others =>'Z');
else
do <= ram( conv_integer (a) );

end if;
end if;
end process;

end Behavioral;


I'll be thankful you help me ...

Thanks & Regards ...

 

[gck]

Block RAM

Block RAM is dual port ram, of which both ports can be clocked different clock. Its special block which works as RAM. There is another type of RAM called distributed RAM formed from CLBs.

 

[hm_fa_da]

Thanks,

are block ram & distributed ram as a separate part and Synthesizer recognizes to use it ?
i mean if we write a code that some of it is working as ram , then synthesizer and ( ISE software ) would extract it from code and use Block ram for that part ? or any code we write is made from only gates in FPGA ?
how about my first question , about design summary ?

 

[echo47]

The xc3s250e contains twelve 18-kilobit dual-port RAM resources. Your design consumes eight of them.

"Equivalent gates" is a strange metric -- useless to most people.
Instead, read the other numbers in your mapper "design summary" report.

They synthesis software will automatically choose distributed RAM or block RAM, or you can override its choice by applying a RAM_STYLE constraint.

To learn more about inferring RAM and other common logic blocks, read the "HDL Coding Techniques" chapter in your "XST User Guide".

 

[hm_fa_da]

i'll go for more information and the XST user guide , however ,a question,
it means that there are some common logic blocks in FPGA , and Synthesizer will recognize to use them or not ?
and if the code didn't use common logic blocks , would use it's gates to make them ?
and what 250K gates stand for in xc3s250e ?
i remember in quartus software , it says how much of the fpga is used in percents , but it is not available in ISE in a simple percent !

how about if my code needs 13 block of ram , then it would use 12 of the block ram and the other one from other resources ? and using other resources will waste ... ?