Questions about how to use casex in Verilog

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billylee

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The following is an example of the casex statement
is this code ambiguous? Thank you!

always @(*) begin
casex (SumMsbSat1[16:13])
4'b0000 : SumMsbSat3 = SumMsbSat1[13:0];
4'b1111 : SumMsbSat3 = SumMsbSat1[13:0];
4'b0xxx : SumMsbSat3 = {1'b0, {13{1'b1}}};
4'b1xxx : SumMsbSat3 = {1'b1, {13{1'b0}}};
default : SumMsbSat3 = SumMsbSat1[13:0];
endcase
end
 

Case statement is prioritized so that it looks fine to me, though you don't need default in this case.
 

thank you for your reply
also my coworker agree with you!

and Merry christmas~!
 
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