I'm new to VHDL and would need advice for a loop. Would it be possible to use a signal instead of the variable z in the following code?
Will it be a problem to use z in a way like in the code because of the read and then write access. I've heard about possible oscillation or things like that.
Here's the code (Of course not functional and only a cutout)
Code VHDL - [expand]
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cordic:process(clk)variable di:std_logic;variable z :std_logic_vector(PA_RES DOWNTO0):=(others=> '0');variable sin_temp, cos_temp :sfixed(1downto-14);beginif(rising_edge(clk)and(enable_cordic='1'))then
z := phase;
sin_temp := sin_init;
cos_temp := cos_init;FOR i in0to12LOOPif(z(PA_RES)='1')then
z :=std_logic_vector(signed(z)+signed(my_Rom(i)));else
z :=std_logic_vector(signed(z)-signed(my_Rom(i)));endif;ENDLOOP;endif;endprocess cordic;
Signals are updated at the end of a process, thus won't work in a loop like this. my_ROM can't be a block RAM, because you can't access multiple memory locations in a single clock cycle.
The rom table will be synthesized as parallel logic in the present code, in so far it works.
But you are synthesizing 13 cascaded adders and multiplexers without any pipelining, so fmax will be rather low. I also assume that the final cordic code will have more arithmetic and can't achieve any reasonable speed without pipelining.