# Questions about for loops in VHDL

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#### Flo89

##### Newbie level 4
Dear expers,

I'm new to VHDL and would need advice for a loop. Would it be possible to use a signal instead of the variable z in the following code?
Will it be a problem to use z in a way like in the code because of the read and then write access. I've heard about possible oscillation or things like that.
Here's the code (Of course not functional and only a cutout)

Code VHDL - [expand]1
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cordic: process(clk)
variable di: std_logic;
variable z : std_logic_vector (PA_RES DOWNTO 0) := (others => '0');
variable sin_temp, cos_temp : sfixed (1 downto -14);
begin
if(rising_edge(clk) and (enable_cordic='1')) then
z := phase;
sin_temp := sin_init;
cos_temp := cos_init;
FOR i in 0 to 12 LOOP
if (z(PA_RES)='1') then
z := std_logic_vector(signed(z) + signed(my_Rom(i)));
else
z := std_logic_vector(signed(z) - signed(my_Rom(i)));
end if;
END LOOP;
end if;
end process cordic;

Thanks a lot!!
Best regards,
Florian

#### FvM

##### Super Moderator
Staff member
Signals are updated at the end of a process, thus won't work in a loop like this.
my_ROM can't be a block RAM, because you can't access multiple memory locations in a single clock cycle.

Flo89

### Flo89

points: 2

#### Flo89

##### Newbie level 4
Thanks for the fast answer!
my_Rom is implemented like this:

Code:
type mem is array ( 0 to 12) of std_logic_vector(PA_RES downto 0);
constant my_Rom : mem := (
0  => "0010000000000000",
1  => "0001001011100100",
2  => "0000100111111011",
3  => "0000010100010001",
4  => "0000001010001011",
5  => "0000000101000110",
6  => "0000000010100011",
7  => "0000000001010001",
8  => "0000000000101001",
9  => "0000000000010100",
10 => "0000000000001010",
11 => "0000000000000101",
12 => "0000000000000011");
Will it work, I didn't really understand the thing with multible momory locations!
Again, thanks in advance!

#### TrickyDicky

##### Advanced Member level 5
That is just a constant declaration. It is how you access it in a process that makes a rom or not.

#### FvM

##### Super Moderator
Staff member
The rom table will be synthesized as parallel logic in the present code, in so far it works.

But you are synthesizing 13 cascaded adders and multiplexers without any pipelining, so fmax will be rather low. I also assume that the final cordic code will have more arithmetic and can't achieve any reasonable speed without pipelining.

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