Questions about character lcd display

[wereiyou]

Hi:
I got some difficulities about character lcd display. Although I write the right DDRAM address to the lcd, but the character doesn't display in the right place. For example, I write 8'h80 to the DDRAM address, it doesn't display in the first position of the upper line. but displays maybe in the 8 position of the upper line. How can I solve this problem. It has troubled me for a long time. My character lcd is fixed on the devleop board and the lcd's contrl chip is hd44780. Thanks everybody!
The bleow is my code(verilog)

module LCD(clk_50hz,lcd_rst,lcd_rw,lcd_rs,lcd_data,lcd_e);

input clk_50hz;
input lcd_rst;

output[7:0] lcd_data;
output lcd_rs;
output lcd_rw;
output lcd_e;

wire[7:0] lcd_data;
wire lcd_rs;
wire lcd_rw;
wire lcd_e;

reg start_finish;
reg init_e;
reg init_rs;
reg init_rw;
reg[7:0] init_data_buf;

reg work_e;
reg work_rs;
reg work_rw;
reg[7:0] work_data_buf;

assign lcd_data = !start_finish? init_data_buf: work_data_buf;
assign lcd_rw = !start_finish? init_rw: work_rw;
assign lcd_rs = !start_finish? init_rs: work_rs;
assign lcd_e = !start_finish? init_e: work_e;

//-------------lcd initialize
reg[3:0] count;
always @(posedge clk_50hz)
if(lcd_rst)
begin
init_rs <= 1'b0;
init_rw <= 1'b0;
count <= 4'b0001;
start_finish <= 1'b0;
init_data_buf <= 8'h00;
init_e <= 1'b0;
end
else
if(!start_finish)
case(count)
4'b0001:
if(!init_e)
init_e <= 1'b1;
else
begin
init_e <= 1'b0;
count <= 4'b0010;
init_data_buf <= 8'h38;
end
4'b0010:
if(!init_e)
init_e <= 1'b1;
else
begin
init_e <= 1'b0;
count <= 4'b0100;
init_data_buf <= 8'h0f;
end
4'b0100:
if(!init_e)
init_e <= 1'b1;
else
begin
init_e <= 1'b0;
count <= 4'b1000;
init_data_buf <= 8'h03;
end
4'b1000:
if(!init_e)
init_e <= 1'b1;
else
begin
init_rs <= 1'b0;
init_rw <= 1'b0;
init_e <= 1'b0;
count <= 4'b0001;
start_finish <= 1'b1;
init_data_buf <= 8'h01;
end
endcase

//------------------------send address and data
reg[1:0] sel;
reg work_finish;
always @(posedge clk_50hz)
if(lcd_rst)
begin
work_e <= 1'b0;
work_rs <= 1'b0;
work_rw <= 1'b0;
sel <= 2'b00;
work_finish <= 1'b0;
work_data_buf <= 8'h00;
end
else
if(start_finish && !work_finish)
case(sel)
2'b00:
if(!work_e)
begin
work_e <= 1'b1;
work_rs <= 1'b0;
end
else
begin
work_e <= 1'b0;
sel <= sel + 1'b1;
work_data_buf <= 8'h83;
end
2'b01:
if(!work_e)
begin
work_e <= 1'b1;
work_rs <= 1'b1;
end
else
begin
work_e <= 1'b0;
sel <= sel + 1'b1;
work_data_buf <= 8'b01001101; //----6D M
end
2'b10: begin
if(!work_e)
begin
work_e <= 1'b1;
work_rs <= 1'b0;
end
else
begin
work_e <= 1'b0;
sel <= sel + 1'b1;
work_data_buf <= 8'h82;
end
2'b11: begin
if(!work_e)
begin
work_e <= 1'b1;
work_rs <= 1'b1;
end
else
begin
work_e <= 1'b0;
work_data_buf <= 8'b01100001; //-----61 a
sel <= 2'b00;
work_finish <= 1'b1;
end
end
endcase
endmodule