Question Regarding VCS Tool??

[aswin123]

how to use vlogan

when we are executing system verilog or verilog programs in VCS ,what are the files are generating.

 

[indomitable12345]

vcs tool log file

when compiling a verilog design using vcs,first a simv file is generated..........then it is compiled to get the vcd/vpd file.........this file can then be used by virsim to see the waveform..........its better to see the vcs user's manual to get better details.....

 

[aswin123]

vcs vcd to waveform

Thanks for u r reply.

VCD means value change dump,VPD means what????

and VPD file is generated after simulation.do u know what this file contains??? and it in ASCII format or BINARY format.

 

[indomitable12345]

vcs vpd dump

vpd file is a waveform dump file just like vcd which is used by the vcs native waveform viewer i.e virsim ......it is more compact and occupies less space than a vcd file........though vcd file is not a compact format,it is the only medium for sharing waveforms between different tools.......

p.s----i forgot to write one thing........the first step is the parsing of design files using vhdlan or vlogan ........

 

[aswin123]

top 10 vcs tools

if u dont mine can u expalin this sentence again......i am unable to understand parsing and vlogan


p.s----i forgot to write one thing........the first step is the parsing of design files using vhdlan or vlogan ........

 

[amnsgk]

vcs debug_pp

>>Posted: 25 Jun 2007 2:47 Post subject: Question Regarding VCS Tool??
when we are executing system verilog or verilog programs in VCS ,what are the files are generating.

VCS flow consists of two steps namely compilation and simulation.

Step One: Compile your design and generate the executable.
%vcs <options> <source_files>
"simv" is the default executable file generated.

Step Two: Simulate the generated executable file
%simv <options>

If you have dumped the signals then you need to use the required compile time options such as debug_pp or debug or debug_all. After simulation, either .vcd or .vpd file will be generated. You can use the latest waveform viewer DVE for debugging. You can refer the VCS Userguide $VCS_HOME/doc/UserGuide/vcs.pdf for more details.

>>p.s----i forgot to write one thing........the first step is the parsing of design files using vhdlan or vlogan ........

Please note that this is for Mixed-HDL simulation. You can refer the VCS Userguide $VCS_HOME/doc/UserGuide/vcsmx_ug.pdf for more details.

Hope this helps.