vcs debug_pp
>>Posted: 25 Jun 2007 2:47 Post subject: Question Regarding VCS Tool??
when we are executing system verilog or verilog programs in VCS ,what are the files are generating.
VCS flow consists of two steps namely compilation and simulation.
Step One: Compile your design and generate the executable.
%vcs <options> <source_files>
"simv" is the default executable file generated.
Step Two: Simulate the generated executable file
%simv <options>
If you have dumped the signals then you need to use the required compile time options such as debug_pp or debug or debug_all. After simulation, either .vcd or .vpd file will be generated. You can use the latest waveform viewer DVE for debugging. You can refer the VCS Userguide $VCS_HOME/doc/UserGuide/vcs.pdf for more details.
>>p.s----i forgot to write one thing........the first step is the parsing of design files using vhdlan or vlogan ........
Please note that this is for Mixed-HDL simulation. You can refer the VCS Userguide $VCS_HOME/doc/UserGuide/vcsmx_ug.pdf for more details.
Hope this helps.