Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question regarding NMOS and ouput

Status
Not open for further replies.

Hellsin

Newbie level 4
Newbie level 4
Joined
Apr 22, 2014
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
29
Capture.JPG



Can any pro out there please guide me to the answer for A and B ?

Thank you very much
 

How much is the threshold voltage?(that is Vt)?
And are both the transistors in saturation/cut off/triode mode of operation?Please specify......
 

Let say the threshold voltage is 0.7V
both trans are in saturation mode
what will be it ?
 

Ok...for saturation mode,equation is..
Vds=Vgs-Vt
0.7-Vs=0.7-Vs-0.7...and solving..
Vs will cancel out...looks like it cannot be solved...or maybe I am wrong.
Are you sure that the drain voltage and the gate voltage is 0.7V..??check again the figure..there could be some mistake(s).
 


Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top