If you set the enable bit low, it will then halt at whatever state it's in.
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PS. This is not a verilog question - this is a digital logic question, which is nothing to do with verilog. You need to go and do a bit more learning about how digital systems work before you write ANY verilog. Verilog is an HDL (hardware description language), so you need to understand the circuit before you write any code. The usualy approach is to draw a diagram of the circuit before you write the HDL.