Indrajit Ghosh
Junior Member level 2
suppose I have instantiated to ipcores c1,c2 in a module suppose called top module.now a control signal activates core c1 and a control signal from core c1 activates c2. Now suppose i include an always block for positive clock cycles and inside it I write some conditional logic where the signal activating core c1 turns off.Now my question is that will the core keep executing itself over and over again till the control signal is activated or will it run only once and the always block will run over and over again?
PS:- I am new in verilog
PS:- I am new in verilog