# question regarding execution of statement in verilog!!

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#### Indrajit Ghosh

##### Junior Member level 2
suppose I have instantiated to ipcores c1,c2 in a module suppose called top module.now a control signal activates core c1 and a control signal from core c1 activates c2. Now suppose i include an always block for positive clock cycles and inside it I write some conditional logic where the signal activating core c1 turns off.Now my question is that will the core keep executing itself over and over again till the control signal is activated or will it run only once and the always block will run over and over again?

PS:- I am new in verilog

#### TrickyDicky

If you set the enable bit low, it will then halt at whatever state it's in.

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PS. This is not a verilog question - this is a digital logic question, which is nothing to do with verilog. You need to go and do a bit more learning about how digital systems work before you write ANY verilog. Verilog is an HDL (hardware description language), so you need to understand the circuit before you write any code. The usualy approach is to draw a diagram of the circuit before you write the HDL.

#### Indrajit Ghosh

##### Junior Member level 2
well I am trying to implement the "DIGITAL LOGIC QUESTION" using verilog...:smile:

#### andre_luis

##### Super Moderator
Staff member
I´m not too familiar with HDL designs, but sounds like related to FSM scope, due each state represents an enable condition to execute each core.

#### TrickyDicky

well I am trying to implement the "DIGITAL LOGIC QUESTION" using verilog...:smile:

Yes - but before you write ANY verilog, you need to know what the digital logic is. Have you drawn a diagram of the circuit? (you dont need verilog for this).

##### Super Moderator
Staff member
Now suppose i include an always block for positive clock cycles and inside it I write some conditional logic where the signal activating core c1 turns off.
This looks like a Verilog question on how an edge triggered always block behaves.

Now my question is that will the core keep executing itself over and over again till the control signal is activated or will it run only once and the always block will run over and over again?
but then you come back with this confusing question. which core are you talking about? the one that sends or the one that receives the turn off signal.

The always block will continually be activated (scheduled) each time the positive edge of the clock arrives.

Code Verilog - [expand]1
always @ (posedge clock) begin /*...some code to execute...*/ end

so whatever outputs that always block generates will continue to be updated every clock edge.

Indrajit Ghosh

Points: 2