[SOLVED] question regarding DDR3 BL8 and addressing in MIG for Virtex6

[syedshan]

Hello every one,

Please answer my query to resolve the confusion. I will refere to the forumanswers here.
Fist of all same usual complain that ug406 looks make things little confused.

Any ways. I am confused about he BL-8 (or BC-4, but not conerned). My DDR3 is 16-bit DDR3 wide.
Hence its payload width is 16, right. Now according to this forum my burst length should be
8*[PAYLOAD_WIDTH]
(I am using Virtex-6 )

Now according to this message my burst length should be . 16*8 , right i.e. 128 bits, but since datawidth is 4*[PAYLOAD_WIDTH] hence 4*16 = 64 bits, so I have to transfer Two-data W0-W1 (according to write path eye-diagram) page 121 (figure 1-62).

I have following questions as well

1. Hence what increament of address should I do. I have to consecutively write data so for that should it be merely
app_add <= app_add + 1; -- note that orientation is (ROW-Bank-COL)
what if bank-row-col

or what... have no clue at all what so ever!!

2. Why is this burst length actually there at the first place, it seems like waste of (7 bits * datawidth ) per each data transfer. As far as I understand is that copy of the same data is copied to 8 locations. But then I came across this line in datasheet...

The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command....
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by [I]A[i:2][/I] when the burst length is set to 4 and by [I]A[i:3][/I] when the burst length is set to 8 (where [I]Ai[/I] is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.

after reading this I am thoroughly confused.

3. my data is 16 bit in itself. so should it be (a/c/ to figure 1-62 or 1-63 either) see image below

W0 = d0 & d1 & d2 & d3 ; --where & denote concatenation and dx are the 16 bit datas; Wwidth = PAYLOAD*4 = 64bit
w1 = d4 & d5 & d6 & d7; --ofcourse this is just for here actual implementation is different in proper vhdl style.

Many thanks in advance

 

[syedshan]

Any one reply!!

atleast qeustion 1 and 3

 

[mrflibble]

Maybe reading this will help a little: **broken link removed**

 

[syedshan]

Thank you for your reply.

I read that already and it is realy useful, but I am uncertain about addressing even now.

I mean to say how can should I increase addressing. The datasheet says that A[2:0] are reserved column bits and rest we can utlize..
But I have seen in the example simulation that address were increased from 0 to 16 to 32 to 48...etc.

I hope am able to tell what I want to

 

[mrflibble]

I am not sure what the problem is. Maybe your confusion comes from byte count vs word count? As in the address is going to be the byte count, and the burst size is more related to data words because, well, data is transfered is word sized chunks.

So you have bursts of 8 words at a time. Which makes perfect sense with the "A[2:0] are reserved column bits". As in 2^3 = 8 burst size. And if you have 16-bit words = 2 bytes ... then you have a burst of 8 words x 16-bits per word, or 8 words x 2 bytes ==> address increment of 16.

Does that help? I am mainly guessing here since I am not sure what the problem is.

 

[syedshan]

I find the answer long ago to my questions long ago and hence just writng the solution here

Hello every one,

1. Hence what increament of address should I do. I have to consecutively write data so for that should it be merely
app_add <= app_add + 1; -- note that orientation is (ROW-Bank-COL)
what if bank-row-col

or what... have no clue at all what so ever!!

The address increment should me app_addr <= app_addr + 8; , this will be same for any orientation since MIG will resolve the address later stage itself

and yes the data is concatenated actually the way I discussed in question.

 

[mrflibble]

I would not have guessed that the problem was "how to increment address by the burst size". ;-) Anyways, problem solved is a good thing.

 

[syedshan]

hehehe...

actually when I was doing the stuff, actually it was really head aching
So I thought it might help others. Even if not they can ask on this post if they have any querry...


any ways when I was typing it was also looking silly...

- - - Updated - - -

hehehe...

actually when I was doing the stuff, actually it was really head aching
So I thought it might help others. Even if not they can ask on this post if they have any querry...


any ways when I was typing it was also looking silly...