Question On test of delta-sigma F-N PLL

[bigworm]

fn-pll

I met with the problem of testing of F-N PLL with 3order mash delta-sigma.
the clk for delta-sigma modulator is 13MHz, which is of the same frequency with reference frequency for PFD. when I measure the spectrum with SA,
I found that it seems to be a integer-N PLL.
when I set a fraction 144.6, vco only gives 144*13=1872M.why?
I thoutht it should be 144.6*13=1879.8M

does this problem result from the 13M clk of delta-sigma, since PLL can't be locked in about 70ns( 1/13M), and the divider ratio changes every 70ns?

Need your help

 

[tlihu]

Plz check if there is any deviation for the reference clock from the nominal 13MHz, i.e., 12.xxx or 13.xxx.

 

[niklas.zhu]

you should not use reference frequency as the clk for delta-sigma modulator
pls use the divided frequency for that clk

 

[bigworm]

yes, the clk for modulator is the divided vco signals
but it seems that the modulator does not work
do you know why?
and if modulator(mash) is working,
how should it be on the SA?

thank you

 

[orley]

There maybe two trouble with your F-N. One is your sigma-delta modulator is sometimes wrong, because its closed-loop means something wrong by my opinion. The other is your divider can't work ideally, especially in swallow counter and program counter and prescaler.

Best Regards!

 

[bigworm]

Thank you for your answer.
I still quite puzzled.
if sigma-delta modulator doesn't work well, I may get another average division ratio other than expected one. but in fact, the pll can't lock at fractional frequency.
do you agree with this?
as for the counter, I quite agree with you. if the counter sometimes works abnormally, PLL may lose the status of LOCK.
can you give me some further advice?