Question On Process Variation For Design

[suria3]

Guys,

I have question here regarding process variation. As we know, during the design phase we will run simulation for our circuit according to Best, Worst and Typical case. My question here is, let say my resistor in my design to vary +/- 10%, does it mean that the 10% variation is already included in the best,worst and typical process. So, when we send design for fabrication, it is assumed the changes on the resistor value is already seen during the process simulation or on the other way around. please get me clear on this matter. Thank you very much.

Suria.

 

[Humungus]

You must account for lot to lot variations and die to di variation on the same wafer. As both kind of variations manifest themselves in the same way you must add them and consider them with a uniform probability distribution. Additionally, you must account for device to device variations (matching) inside the same die and one device close to the other.

Normally, the fab will give you information about both kind of variations. Up to you to implement a suitable model that represents both variations.


If you are designing analog circuits, simulating at FF, SS and TT corners is not enough. At least you should include FS, and SF corners. Anyway this wont give you a realistic idea. You must perform Monte Carlo simulations to really validate your design.

F= fast; FF= N and P transistors are fast
S= slow
T= typical

 

[maddy]

To add to Humungus's note, the no. of Monte Carlo runs to see a process spread will also be recommended by the Foundry. In an IBM process, I believe it was 30 runs. Sometimes, it may not be possible to have 100 runs in MC because of time and memory.

Madhav

 

[sankudey]

Some real points:
As mentioned in above two posts; all these are necessary. But definitely these costs a lot; may be in terms of simulation time or other way around. One practical approach could be the following.

By running the typ/bcs/wcs file and corners the gros or absolute variation is taken care. But some thing is still hidden. That is called "MISMATCH" or "RELATIVE MISMATCH". For a differential pair which leads to offset, for a current mirror which lead to two different current. SOme times these points are proved to be potential; not even degrading the performance the whole system, but also could make it NON-FUNCTIONAL.

A practical way to handle it is studying the relative mismatch at smaller block level. This study could be made first by analytical means and accordingly offset, gain requirement, accuracy etc. could be cal culated. According to the analysis the circuit is designed. Now, when a small block's design is complete, you have to get confirmed that it is enough robust to device mismatch which was proven in the analysis. This is done by simulation. By theory, you may need to go for putting by hand the mismatches in the device and simulate. But the total no. of permutation/combination would be much high stopping it from real checking. Thus, you start from the input and travel to the output through the signal path. As going from ip to output, you add the % of mismatch (should be provided by foundry for the required sigma value) in a manner that the error are additive. So at the output you find that the worst possible case case mismatch output is coming. Thus you have reduced the total no of permutations to one configuration only. For some topologies the above one could be more than one; say 3/4. Thus it is still possible to handle by hand in simulation.

Now you have designed a block which is mismatch tolerant. When you are connecting them in the system, you really have not the option to do the same again. Here; I suppose; a analytical approach would be good enough when all block's error are taken in additive fashion.

What I described above may be proven fruitful those are not having the option running Monte Carlo simulation at circuit level. Again some times this is taken as the best way to prove that the blcok will at least be functional even at worst condition, which information can not be given by Monte Carlo Simulation. Montecarlo simualtion gives % of parts going to work which is a statistical data.

Gd Luck..
sankudey

 

[bagi]

some body can please upload a book on monte carlo simualtion