unreal2695
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Hey all:
I have a question on the LDO load transient (P-Pass LDO, internally compensated). According to most of the literature, the voltage undershoot/overshoot with a fast load transient can be calculated as V=(I/(C*BW)), where I is the load variation, C the output buffer capacitance and BW the unity gain frequency of the loop gain. However in my simulation, the voltage droop from no load to full load is much less than what is calculated. What I observe also is that the EA output changes right after the output voltage starts to decrease.
My question is then
(1) Is the reciprocal of the closed loop bandwidth corresponds not to the discharging time of the output capacitor with the load current, but the whole settling time?
I think this somehow makes sense as the closed loop bandwidth tells only the small signal behavior, but a load transient basically starts with large signal (maybe slew rate dominates more at this stage?).
(2) If this is the case, then how to select the closed-loop bandwidth and the buffer capacitor size so that I can meet the specification with voltage overshoot/undershoot? Is this done by trail and error or there is some kind of rule of thumb?
Thanks a lot !!!!
I have a question on the LDO load transient (P-Pass LDO, internally compensated). According to most of the literature, the voltage undershoot/overshoot with a fast load transient can be calculated as V=(I/(C*BW)), where I is the load variation, C the output buffer capacitance and BW the unity gain frequency of the loop gain. However in my simulation, the voltage droop from no load to full load is much less than what is calculated. What I observe also is that the EA output changes right after the output voltage starts to decrease.
My question is then
(1) Is the reciprocal of the closed loop bandwidth corresponds not to the discharging time of the output capacitor with the load current, but the whole settling time?
I think this somehow makes sense as the closed loop bandwidth tells only the small signal behavior, but a load transient basically starts with large signal (maybe slew rate dominates more at this stage?).
(2) If this is the case, then how to select the closed-loop bandwidth and the buffer capacitor size so that I can meet the specification with voltage overshoot/undershoot? Is this done by trail and error or there is some kind of rule of thumb?
Thanks a lot !!!!