Active Load for 500VDC/10A , for resistive load

[abicash]

Hi

I am trying to figure out specs to design the following active load circuit to drive a controlled current through a resistive load.

Load resitance : 50 ohms
Current through Load : 10A dc (programmable from 1A to 10A)
Effectively V-Load min : 500 Vdc
Max time of current flow : 1 second

I am trying to design such a circuit as per the attached schematic.
The first stage of the opamp sets the current reference obtained from a microcontroller DAC output.
The second stage is the actual drive and compares the instantaneous current across the sense resistor with the set current.

I have trouble identifying a capable DC MOSFET (or number of parallel DC MOSFETS) with a good enough SOA.
IXTK8N150L is one which I found to be adequate and it has a SOA at 500V to be around 1A , @60C. So I would need at least 10 no's in parallel.
They would probably need separate drives for each.

Am I going in the right direction?

 

[KlausST]

Hi,

I have a lot of questions.
(Btw: The picture is so blurry one can not read numbers. Use .png picture format)

Load resitance : 50 ohms

What dies this mean?
An active load automatically adjusts it´s resistance to the input voltage and current setpoint.

Effectively V-Load min : 500 Vdc

What does "effectively" mean here?
In case the input voltage is not DC: What´s the expected voltage waveform and frequency?
And why it is specified as "min" .. I rather expect it to be the "max" value.

***
Schemaitc:
I don´t see the need for the first stage. When I have a microcontroller and a DAC I´d surely do the gain calibration in software ..to avoid an external pot.
Also i´d avoid the voltage limiting diode directly connected to the output. When active the output is short circuited and may lead to overheat and destruction of the OPAMP.
(Without knowing which OPAMP you use. Please post a link to the OPAMP datasheet)

I think the capacitor at the non inverting input is coutner productive. It increases noise and maybe even causes oscillations. I´d rather connect it across the pot.

Also: driving a low impedance capacitove laod may cause instability.

2nd stage:
* the feedback connection surely is wrong. It shold be connected at the upper leg of the shunt.
***
Stability, ruggedness.. depends on heatsink, OPAMP type, load type and connections, and a lot of other parameters.
The worst case I think is when the DAC demands hhigh current while the load is disconnected. In this case the output of the 2nd stage is saturated at the supply voltage. Thus the input stage is saturated, too. If now you connect a very low ohmic load ... the regulation loop needs some time to come out of saturation and to get into regulation mode. During this time a critcal high current may cause the transistors to be destroyed.

To find a good solution .. we need to know your requirements about overshoot timing and and expected input frequency range frequency first.

****
I´d add a useful feature:
A comparator that monitor the 2nd stage output voltage. In case it is over a threshold (determined by max current, transistor type, shunt value) then light up a red ERROR LED. (Output current is NOT the expected setpoint current)

Klaus

 

[dick_freebird]

I recommend a set of parallel switched resistors controlled however you like. I've built "load slammers" for DC-DC testing this way.

Linear control loops are too slow and easy to fool, IME, for high slew rate outputs. Their control loops may "bicker" too.

 

[abicash]

Hi,

I have a lot of questions.
(Btw: The picture is so blurry one can not read numbers. Use .png picture format)


What dies this mean?
An active load automatically adjusts it´s resistance to the input voltage and current setpoint.


What does "effectively" mean here?
In case the input voltage is not DC: What´s the expected voltage waveform and frequency?
And why it is specified as "min" .. I rather expect it to be the "max" value.

***
Schemaitc:
I don´t see the need for the first stage. When I have a microcontroller and a DAC I´d surely do the gain calibration in software ..to avoid an external pot.
Also i´d avoid the voltage limiting diode directly connected to the output. When active the output is short circuited and may lead to overheat and destruction of the OPAMP.
(Without knowing which OPAMP you use. Please post a link to the OPAMP datasheet)

I think the capacitor at the non inverting input is coutner productive. It increases noise and maybe even causes oscillations. I´d rather connect it across the pot.

Also: driving a low impedance capacitive laod may cause instability.

2nd stage:
* the feedback connection surely is wrong. It shold be connected at the upper leg of the shunt.
***
Stability, ruggedness.. depends on heatsink, OPAMP type, load type and connections, and a lot of other parameters.
The worst case I think is when the DAC demands hhigh current while the load is disconnected. In this case the output of the 2nd stage is saturated at the supply voltage. Thus the input stage is saturated, too. If now you connect a very low ohmic load ... the regulation loop needs some time to come out of saturation and to get into regulation mode. During this time a critcal high current may cause the transistors to be destroyed.

To find a good solution .. we need to know your requirements about overshoot timing and and expected input frequency range frequency first.

****
I´d add a useful feature:
A comparator that monitor the 2nd stage output voltage. In case it is over a threshold (determined by max current, transistor type, shunt value) then light up a red ERROR LED. (Output current is NOT the expected setpoint current)

Klaus

Hi Klaus

Thanks for the feedback.
Please find the updated schematic attached for better viewing.
The parts which you mentioned are DNP, but provisioned just in case!
Here is the opamp datasheet

I will explain the project a bit.

I require to pass a programmed constant current through a fixed 50 ohm load. Thus the voltage requirement is 500Vdc at least.
Current is in range of 1 to 10A and for that I have used the DAC from the Microcontroller to supply the reference.

I need to pass this voltage (current) through a MOSFET to the load resistance for a time period of 1 second.
The load resistance is populated from the 500Vdc to the drain of the MOSFET.
( I corrected the feedback loop. It was a typo during sch drawing)

I have successfully made such a circuit last year , but it was for 100Vdc and 5A. For that I had used IXTK90N25L2.
I am looking to upscale this to 500Vdc and 10A.
For this I need to identify an appropriate MOSFET as I have mentioned earlier having a robust SOA.
Unfortunately , the part I mentioned : IXTK8N150L is insufficient and so I may have to parallel at least 10 nos.
There will be a need for a sufficient drive as well for each of this MOSFET.

Kindly advise.

 

[KlausST]

Hi,

general terminology question:
Why do you call it "active load"? Isn´t your circuit function a "constant current sink"?

***
Datasheet: It´s very important for you to read the datasheet.

***

I require to pass a programmed constant current through a fixed 50 ohm load.

If it is a "fixed 50 Ohms load" why the handstand with the current source? ... a voltage source would be simpler and would do the same.
If there is a reason for using a current source then tell us.
(usually one uses a constant current sink (source) when the resistance is unknown, not fixed, drifting ...)

hus the voltage requirement is 500Vdc at least.
Current is in range of 1 to 10A and

Correct me if I´m wrong:
If the current is 1A.. 10A .. and the resistance is 50 Ohms. Then the load voltage is 50V (min) to 500V (max)

If you use 500V min ... then all other voltages are higher than 500V and thus cause a current higher than 10A .. and you never are able to achieve 1A.

****
Schematic:
What´s the use of R15, R16, R18, R20, R24, C29?
When you know there are several transistors in parallel ... I recommend to draw this into the schematic. So everyone who sees the schematic immediately has this complete information.
Otherwise it´s ambiguous: schematic says so, text otherwise .. which one is true?

The parts which you mentioned are DNP, but provisioned just in case!

What does this mean?
* we completely should ignore them?
* As soon as yo use them: you open a new thread to aks about problems (we currently know they exist)
* We shoud treat and discuss about them as "existing" to avoid future problems?

*****
Indeed from my experience ... You may have your ideas with the resistors and the DNP parts. We don´t know .. and there is a good chance that you don´t know either ... after a year. And some of the parts are crtical and don´t follow datasheet regulations.
Thus my recommendation (not meant to force you):
If you don´t want to use them: remove them from the schematic/PCB.
If you expect to use them: follow the datasheet rules so you can safely add them later. Best if you already add informations as text to the schematic.


****

There will be a need for a sufficient drive as well for each of this MOSFET.

Did you do some calculations? Or did you do a simulation?

Your circuit shows an OPAMP output (which is rather low impedance) .. then you use a 1k series resistor to make the signal weak ... but the same time you are worried about the weakness of the signal. Please explain the ideas behind.

***
Regarding SOA. I see you did understand SOA chart. Is there still anything you need to know in detail?

**
Still missing a lot of informations (like timing, frequency .. and a lot more ..) written in my post#2

Klaus

 

[abicash]

Hi,

general terminology question:
Why do you call it "active load"? Isn´t your circuit function a "constant current sink"?

***
Datasheet: It´s very important for you to read the datasheet.

***


If it is a "fixed 50 Ohms load" why the handstand with the current source? ... a voltage source would be simpler and would do the same.
If there is a reason for using a current source then tell us.
(usually one uses a constant current sink (source) when the resistance is unknown, not fixed, drifting ...)


Correct me if I´m wrong:
If the current is 1A.. 10A .. and the resistance is 50 Ohms. Then the load voltage is 50V (min) to 500V (max)

If you use 500V min ... then all other voltages are higher than 500V and thus cause a current higher than 10A .. and you never are able to achieve 1A.

****
Schematic:
What´s the use of R15, R16, R18, R20, R24, C29?
When you know there are several transistors in parallel ... I recommend to draw this into the schematic. So everyone who sees the schematic immediately has this complete information.
Otherwise it´s ambiguous: schematic says so, text otherwise .. which one is true?


What does this mean?
* we completely should ignore them?
* As soon as yo use them: you open a new thread to aks about problems (we currently know they exist)
* We shoud treat and discuss about them as "existing" to avoid future problems?

*****
Indeed from my experience ... You may have your ideas with the resistors and the DNP parts. We don´t know .. and there is a good chance that you don´t know either ... after a year. And some of the parts are crtical and don´t follow datasheet regulations.
Thus my recommendation (not meant to force you):
If you don´t want to use them: remove them from the schematic/PCB.
If you expect to use them: follow the datasheet rules so you can safely add them later. Best if you already add informations as text to the schematic.


****

Did you do some calculations? Or did you do a simulation?

Your circuit shows an OPAMP output (which is rather low impedance) .. then you use a 1k series resistor to make the signal weak ... but the same time you are worried about the weakness of the signal. Please explain the ideas behind.

***
Regarding SOA. I see you did understand SOA chart. Is there still anything you need to know in detail?

**
Still missing a lot of informations (like timing, frequency .. and a lot more ..) written in my post#2

Klaus

Hi Klaus

Appreciate the time you took to reply to my post. Thank you.

I understood and agree with most of your suggestions now.
I also missed conveying a very important point , that the intention to use CC is that the load could be variable as well. Min 1 ohm - Max 50ohm.
So the mention that min 500Vdc is required is WRONG on my part. It should be max 500Vdc.
I apologise for all of the above.

Regarding the output stage driving the opamp , I had used another MOSFET like a darlington to drive the main MOSFET. I did not draw this in to this sch as I thought my question was only regarding the concept of current sharing and SOA for the main MOSFET.

About your question of timing and frequency: This is a one time event , on-demand and asynchronous.

I will draw a more complete sch as suggested and come back soon.
Thanks for all the support.

 

[FvM]

Consider that SOA graph is specifying maximum rating (involving 150 °C junction temperature). Some additional margin would be suggested for reliable operation.

Due to Vgs,th variation of transistors, you need either individual current control ampifiers or large current balancing source resistors.
Gate driver current capability has to be chosen according to intended current source bandwidth which wasn't yet specified. I'd also optimize current controller/driver circuit and frequency compensation in simulation. MOSFET Cdg makes current source frequency behaviour depend on load impedance. Check that it's stable with largest load impedance, including possible parasitic load inductance.

 

[dick_freebird]

Depending on undisclosed / undeveloped requirements
perhaps you really want a DC-DC (switching) approach.

Look at what's going on with "regenerative loads" for
high power test. They make a DC-DC depend off the
article under test, control its input current while it
pumps "whatever" back to the line or the input filter
of something hungry. Free electricity (you pay up
front, natch).

Stand that on its head, chop the MOSFET instead of
linear drive (their intended mode, for which they are
far better suited) and add an inductor, maybe a catch
diode and there's your guts.

You could do a PFM solution with a comparator, a
retriggerable one-shot and a gate driver plus those
FETs.

If you could stand a little base current error (or
take it out of the readings) old school discrete bipolars
are meant for linear highly dissipative operation.
You might think about using a linear MOSFET in
a pseudo-Darlington with a high-watt NPN or several
if there's somebody forcing you into using MOSFETs.
You really want something that will not burn the
channel when operating in a region where that's getting
the concentrated power dissipation (HV, on hard, it's
the drift region that soaks up power and the channel
is minimum resistance; it's "throttling" that
switching MOS may not be made for (making the
little channel / neck, furthest from the heat removal,
take all the heat). The Pdiss rating paradigm is for
switching (between two states where power is
spread well throughout the device volume) in
most cases, aside from devices made for linear
applications. Check out RF LDMOS maybe, for a
1A FET driving a couple power NPNs.

At 1 second your usual ms ramp times ought to
not be a concern. You can play with control, fSW,
upstream power sources. A lucky find in the power
supply department that you can "hijack some test
points" and repurpose might save you all kinds of
effort.