Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question on 2nd Order Sigma-Delta ADC (switched cap)

Status
Not open for further replies.

neoflash

Advanced Member level 1
Joined
Jul 2, 2005
Messages
492
Helped
10
Reputation
20
Reaction score
2
Trophy points
1,298
Activity points
4,759
Hi,

I have a question on a design of 2nd Order Sigma-Delta ADC (switched cap). The schematic is attached on the message.

The question is that the signal transfer function should not be the same as Z-2 as stated in the text book.

The problem stems from the two integrators. Both of the integrators has a
TF = Z-1 / (1-Z-1), which contains a delay. Therefore it is different from standard model of 2nd order mod whose 1st stage integrator doesn't have delay (Z-1).

I'm confused with this since this design is taken from EE247 lecture notes of Berkley. Wish people could help me understand it.
 

hi,
It doesn't matter that Signal transfer function is z^(-1) or z^(-2).
 

As casol suggested it doesn't matter if the STF is either z^-1 or or z^-2 but the additional delay in the signal path will also alter the Noise Transfer Function. The only way to know is to derive it. Just assume e(n) (quantisation noise) as 0 and derive the noise transfer function. You'll find that the NTF is not the same as that of the ideal 2nd order sigma-delta modulator.

So what can we do to make the NTF ideal? we use two scaling constants a and b in the feedback paths such that the NTF gets closer to the ideal one.

The ideal 2nd order circuit was modified for practical purposes.

Hope I am clear.

EDIT: Sorry, I made a mistake. When you derive the NTF you must set the input x[n] to 0 and derive it for y[n]/e[n] where y[n] is the ouptut and e[n] is the linearised quantisation noise.
 

    neoflash

    Points: 2
    Helpful Answer Positive Rating
due to the addittional delay in the practical model the voltage ranges at the output of the integrators increase, so we reduce the gain of the integrator. but if we observe it carefully it is like pipe lining after steady state it takes only one delay but swing is the main thing to look at. so we have restrictions all over.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top