Question of resistance analysis on Powernet

[jswan]

Hi,

I'm having a hard time analyzing resistance on powernet.
The IC that I'm designing is long-thin, and powered from center only.
Thus, analyzing the value and the difference of resistances on the edges are important.



Here's a question.
There is an option to report Point-to-Point resistance in CalibrePEX.
I tried to use it but there's a big problem.
The stupid tool may calculate the resistance from TP(Test Point) to not power pads which parallelly connected but one of the power pads, and I have no idea which pad used in the calculation.

I think the option of point-to-point resistance calculation is literally only for point-to-point.

The extracted parasitic netlist has no problem. So, I do simulation to get the value of resistance, which takes too many time.

Is there any other way to do that?

Thank you in advance.

 

[timof]

Hi -

resistance verification of power nets is a very common task, that has not been properly automated through EDA tools so far.

Recently, a new tool/ functionality - called Rmap - has been reported, that seems to be ideal for the power net verification:

https://www.siliconfrontline.com/wp-content/uploads/2015/05/RMAP-software-for-resistance-verification-of-power-nets-and-ESD-protection-structures.pdf

This tool calculates resistances from pad or several pads (shorted together) to all points on power net, and show the results as resistance color map - then capturing layout mistakes is really easy.