I know I have to design a synchronizer with 2 F.F to pass one signal comes from low frequency clock domain to high frequency clock domain. But If a signal comes from A clock domain with fixed clock frequency must be passed to B clock domain. And clock of B clock domain is adjustable. It's frequency can be faster than A clock domain's frequency Or It's frequency can be slower than A clock domain's frequency. What kind of synchronizer is suit for this situation?
Thanks.
You have to use a structure with:
- a request signal
- a grant signal
The sending procedure then is managed by a FSM
You can request a new transmit from the domain A to the domain B only if you are sure the first data has been well tranferred.
A grant signal can be a double FF clocked signal (on clock B) which go back to domain A with a double FF (on clock A).