b_kkn
Newbie level 2
Hi all,
According to my understating, all procedural blocks are running in parallel.
Please have a look at this simple verilog code. This is generating a clock and works fine.
--------------------------------------------------------------------
module test;
reg clk;
initial begin
clk=0;
end
always clk = #10 ~clk;
endmodule
--------------------------------------------------------------------
Look at following code similar to above one but always block comes before initial black. with this code i get x in the clock line. What is the difference...
According to my understanding Initial and always blocks are running simultaneously it should not make any difference.
--------------------------------------------------------------------
module test;
reg clk;
always clk = #10 ~clk;
initial begin
clk=0;
end
endmodule
--------------------------------------------------------------------
Could any one help me to understand this issue?
Kind Regards.
According to my understating, all procedural blocks are running in parallel.
Please have a look at this simple verilog code. This is generating a clock and works fine.
--------------------------------------------------------------------
module test;
reg clk;
initial begin
clk=0;
end
always clk = #10 ~clk;
endmodule
--------------------------------------------------------------------
Look at following code similar to above one but always block comes before initial black. with this code i get x in the clock line. What is the difference...
According to my understanding Initial and always blocks are running simultaneously it should not make any difference.
--------------------------------------------------------------------
module test;
reg clk;
always clk = #10 ~clk;
initial begin
clk=0;
end
endmodule
--------------------------------------------------------------------
Could any one help me to understand this issue?
Kind Regards.