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Question for verilog experts!

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b_kkn

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Hi all,

According to my understating, all procedural blocks are running in parallel.

Please have a look at this simple verilog code. This is generating a clock and works fine.

--------------------------------------------------------------------
module test;
reg clk;

initial begin
clk=0;
end

always clk = #10 ~clk;

endmodule
--------------------------------------------------------------------

Look at following code similar to above one but always block comes before initial black. with this code i get x in the clock line. What is the difference...
According to my understanding Initial and always blocks are running simultaneously it should not make any difference.
--------------------------------------------------------------------
module test;
reg clk;

always clk = #10 ~clk;

initial begin
clk=0;
end

endmodule
--------------------------------------------------------------------

Could any one help me to understand this issue?

Kind Regards.
 

sudhirkv

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All procedural blocks are exceuted in parallel specifies that when you wirte a synthesizable verilog or vhdl code it works in parallel. But the simulation software excecutes only sequentially.
 

mytechface

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i agree with sudhirkv.

but the fundamental issue here is the difference between

#10 clk = ~clk;

and

clk = #10 ~clk;

if you've usedthe former, then it does not matter where the initial block is, while the latter, as you've realized is more sensitive to it. i suggest you use the former for what you intend to do ;-)
 

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