Look at following code similar to above one but always block comes before initial black. with this code i get x in the clock line. What is the difference...
According to my understanding Initial and always blocks are running simultaneously it should not make any difference.
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module test;
reg clk;
All procedural blocks are exceuted in parallel specifies that when you wirte a synthesizable verilog or vhdl code it works in parallel. But the simulation software excecutes only sequentially.
but the fundamental issue here is the difference between
#10 clk = ~clk;
and
clk = #10 ~clk;
if you've usedthe former, then it does not matter where the initial block is, while the latter, as you've realized is more sensitive to it. i suggest you use the former for what you intend to do ;-)