i'm simulating delta sigma modulator with 1.5-bit (or 3-level) quantizer, but i found out its SNR is even lower than the 1-bit quantizer. what's wrong with it?
Why use 1.5bits quantizer? Is there any advantanges?
for 1.5 bits quantizer, the output only have three states? Do you have any post process on the output of the quantizer?
Why use 1.5bits quantizer? Is there any advantanges?
for 1.5 bits quantizer, the output only have three states? Do you have any post process on the output of the quantizer?
i'm simulating delta sigma modulator with 1.5-bit (or 3-level) quantizer, but i found out its SNR is even lower than the 1-bit quantizer. what's wrong with it?
Well, I use VerilogA/AMS and when simulating a 3 step quantizer I get more SNR than when using only two levels. I don't really know why it would not work in Matlab. Are you using Simulink?
Does your simulation models include DAC non-linearity? If yes, the 1.5 level DAC may cause performance degradation since it is not inherently linear as the 1 bit solution.
When you said that the SNR was lower for 1.5 bit, you probably were refering to DR, since peak SNR is higher for 3 level ADC according to your image.