[Question] Delta Sigma with Multi-bit Quanitzer

[currentmirror2000]

linear 1.5bit delta sigma

Hi all,

i'm simulating delta sigma modulator with 1.5-bit (or 3-level) quantizer, but i found out its SNR is even lower than the 1-bit quantizer. what's wrong with it?

please see attached figure.

Thanks in advance!
c.m.

 

[sixth]

1.5bit sigma delta

Why use 1.5bits quantizer? Is there any advantanges?
for 1.5 bits quantizer, the output only have three states? Do you have any post process on the output of the quantizer?

 

[currentmirror2000]

how many levels are there for this quanitzer

Why use 1.5bits quantizer? Is there any advantanges?
for 1.5 bits quantizer, the output only have three states? Do you have any post process on the output of the quantizer?

for 1.5-bit quantizer, there are only 3 states: +/-1 and 0 (normalized to the feedback)

what do u mean by 'post process'? decimation filter? no, i collected the output bit stream and do fft in matlab.

c.m.

 

[okguy]

Hi all,

i'm simulating delta sigma modulator with 1.5-bit (or 3-level) quantizer, but i found out its SNR is even lower than the 1-bit quantizer. what's wrong with it?

I also did the matlab simulation and also found out that 1.5bit is worst than 1 bits !
Does anyone know why ?

 

[okguy]

Did anyone has ever designed 1.5bits sigma-delta ADC ?

 

[svensl]

Did anyone has ever designed 1.5bits sigma-delta ADC ?

Well, I use VerilogA/AMS and when simulating a 3 step quantizer I get more SNR than when using only two levels. I don't really know why it would not work in Matlab. Are you using Simulink?

 

[analogy]

Does your simulation models include DAC non-linearity? If yes, the 1.5 level DAC may cause performance degradation since it is not inherently linear as the 1 bit solution.

When you said that the SNR was lower for 1.5 bit, you probably were refering to DR, since peak SNR is higher for 3 level ADC according to your image.