Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Question] Delta Sigma with Multi-bit Quanitzer

Status
Not open for further replies.

currentmirror2000

Member level 4
Joined
Dec 21, 2004
Messages
77
Helped
6
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
798
linear 1.5bit delta sigma

Hi all,

i'm simulating delta sigma modulator with 1.5-bit (or 3-level) quantizer, but i found out its SNR is even lower than the 1-bit quantizer. what's wrong with it?

please see attached figure.

Thanks in advance!
c.m.
 

sixth

Member level 4
Joined
Feb 16, 2006
Messages
70
Helped
10
Reputation
20
Reaction score
0
Trophy points
1,286
Activity points
2,118
1.5bit sigma delta

Why use 1.5bits quantizer? Is there any advantanges?
for 1.5 bits quantizer, the output only have three states? Do you have any post process on the output of the quantizer?
 

currentmirror2000

Member level 4
Joined
Dec 21, 2004
Messages
77
Helped
6
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
798
how many levels are there for this quanitzer

sixth said:
Why use 1.5bits quantizer? Is there any advantanges?
for 1.5 bits quantizer, the output only have three states? Do you have any post process on the output of the quantizer?

for 1.5-bit quantizer, there are only 3 states: +/-1 and 0 (normalized to the feedback)

what do u mean by 'post process'? decimation filter? no, i collected the output bit stream and do fft in matlab.

c.m.
 

okguy

Full Member level 6
Joined
Mar 1, 2002
Messages
360
Helped
15
Reputation
30
Reaction score
9
Trophy points
1,298
Location
China
Activity points
2,650
currentmirror2000 said:
Hi all,

i'm simulating delta sigma modulator with 1.5-bit (or 3-level) quantizer, but i found out its SNR is even lower than the 1-bit quantizer. what's wrong with it?

I also did the matlab simulation and also found out that 1.5bit is worst than 1 bits !
Does anyone know why ?
 

okguy

Full Member level 6
Joined
Mar 1, 2002
Messages
360
Helped
15
Reputation
30
Reaction score
9
Trophy points
1,298
Location
China
Activity points
2,650
Did anyone has ever designed 1.5bits sigma-delta ADC ?
 

svensl

Full Member level 1
Joined
Mar 25, 2005
Messages
99
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
2,202
okguy said:
Did anyone has ever designed 1.5bits sigma-delta ADC ?

Well, I use VerilogA/AMS and when simulating a 3 step quantizer I get more SNR than when using only two levels. I don't really know why it would not work in Matlab. Are you using Simulink?
 

analogy

Newbie level 4
Joined
Aug 12, 2006
Messages
5
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,327
Does your simulation models include DAC non-linearity? If yes, the 1.5 level DAC may cause performance degradation since it is not inherently linear as the 1 bit solution.

When you said that the SNR was lower for 1.5 bit, you probably were refering to DR, since peak SNR is higher for 3 level ADC according to your image.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top