EDALIST's answer sounds right, but if you want to understand timing constraints and errors, I have just the thing for you...
Here is a link to a SUPERB document describing static timing in Xilinx devices, how to set up constraints and what they do. It also covers the error messages and the timing reports so that you can optimise your logic. **broken link removed**
If not clock then atleast there will be one common signal connected to both the blocks....and the STA tool will show that path... you may see that in the unconstraint path report...