the following is the code using generate,endgenerate to achieve an n bit adder. For now, the code sets n=4 thus having a 4 bit adder. The code is working fine.
As you can see in the code, there is no timescale used, I would like each sample to be 100ns long in the waveform viewer. I added the modifications (in red) but the code could not compile. How should I adjust the timescale settings to achieve what i want?
Oh ok. I think I replied before, without reading your full post.
If you want to put the delay in inputs then cant you do it in the testbench code or waveform?
Putting a 100 ns delay in the generate statement doesnt make much sense to me. I may be wrong too, since I am not much into Verilog.