Question about verilog timescale settings.

[qtommer]

hi there,

the following is the code using generate,endgenerate to achieve an n bit adder. For now, the code sets n=4 thus having a 4 bit adder. The code is working fine.
As you can see in the code, there is no timescale used, I would like each sample to be 100ns long in the waveform viewer. I added the modifications (in red) but the code could not compile. How should I adjust the timescale settings to achieve what i want?

thanks alot


`timescale 1ns/1ns

module nbitadder(Cout,Sum,A,B,Cin);
    
    parameter   SIZE=4;
    
    output[SIZE-1:0] Sum;
    output Cout;
    input [SIZE-1:0] A;
    input [SIZE-1:0] B;
    input Cin;    
    
    wire [SIZE:0] w;
    
    genvar i;
    
    assign  w[0]=Cin;
    assign Cout=w[SIZE];
    
    generate
    for(i=0;i<SIZE;i=i+1)
    [COLOR="red"][B]#100;[/B][/COLOR]
       begin:add
            wire n1,n2,n3;
             xor g1 (n1, A[i], B[i]);
             xor g2 (Sum[i], n1, w[i]);
             and g3 (n2, A[i], B[i]);
             and g4 (n3, n1, w[i]);
             or  g5 (w[i+1], n2, n3);
        

             
         end
         
    endgenerate

endmodule

 

[vipinlal]

Try `timescale 1ns/1ps.

 

[qtommer]

hi thanks for your reply

tried it, the same error still occurs...
** Error: ~~~~~ v(23): near "#": syntax error, unexpected '#'

 

[vipinlal]

Oh ok. I think I replied before, without reading your full post.

If you want to put the delay in inputs then cant you do it in the testbench code or waveform?
Putting a 100 ns delay in the generate statement doesnt make much sense to me. I may be wrong too, since I am not much into Verilog.

 

[wsong0210]

It is simply syntex error.
You cannot put delay like this.
Nothing can be inserted between "for ()" and "begin"

I dont understand the meaning of your "sample"
Cannot you just delay it in your test bench?

 

[qtommer]

hey thank you all for the replies..
indeed i did it in testbench and everything works now..thank you all for your help!