Question about Verilog code

[aobosong]

Hello

It is probably common knowledge but I don't know what to Google:

I have this snippet of Verilog code here I want to convert to VHDL:

reg [8:0] error;
reg [11:0]  b1;
b1 = {{3{error[8]}},error};

Thanks!

 

[FvM]

You'll want to review concatenation and replication statement syntax.

As far as I'm aware of, there's no similar repeat (replication) operator in VHDL, so you'll write

b1 <= error(8) & error(8) & error(8) & error;

 

[dave_59]

By the way, what the code is doing is called sign extension and can be easily written in SystemVerilog with

b1 = signed'(error);

In VHDL this would look like

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
[...]
b1 <= SXT(error, b1'LENGTH);

 

[FvM]

In VHDL this would look like

Yes, a sign extension function is in fact the more elegant way in this case. I admit that I wasn't looking for the meaning of the concatenation operation.

 

[permute]

I'm not sure if these work together, but VHDL also has a form of replication.

(0 to 2 => error(8)) & error

Though I think I put this on two lines, assigning one signal slice to (others => error(8)), and the other slice to error.

In this case, sign extend seems better suited though.

 

[TrickyDicky]

By the way, what the code is doing is called sign extension and can be easily written in SystemVerilog with

b1 = signed'(error);

In VHDL this would look like

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
[...]
b1 <= SXT(error, b1'LENGTH);

With standard VHDL you need the resize() function.