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question about transmission gate

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simon0123

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HI

i would like to ask why transmission gate has a wider swing when using transmission gate uesd as switch?

thanks
 

saiaditya

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Hi,

If you look at NMOS (with gate connected to vdd), it has a very low RON for low input values and RON increases as the input increases. Similarily PMOS (with gate grounded) has low RON for input voltages near vdd and RON increases as input voltage decreases.

So when you use a transmission gate with nmos and pmos in parallel, by appropriate sizing you can have a small RON across wide input range, thus effectively acting as a (close to) ideal switch.

Hope it answers your question
 

yadavvlsi

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NMOS can pull-down output to 0V but it can pull-up maximum to VDD-Vtn. So it is bad-1 and good-0 switch. PMOS can pull-up output to VDD but it can pull-down to Vtp. So it is bad-0 but good-1 switch. Vtn,Vtp are threshold voltage for NMOS and PMOS respectively. Transmission gate uses combination two. When input is ZERO it is passed through NMOS and when input is high it passed through PMOS. So you get full swing.
 
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