question about to disconnect the loop of bandgap please help

[tedd]

AS shown in the attachment is the common used bandgap, i want to simulate ac response to gain PM, when i disconnect the input of amplifier (X OR Y). the transfer function has positive sign and the PHASE of the open loop gain is from 0 to 180 when frequency is incresing. but when disconnect the gate of the PMOS transistors (Z node), the transfer function has minus sign, and the PHASE of the open loop gain is from 180 to 0. It seems incorrect. why does this accurs???
thank you very much [/url]

 

[tedd]

I alredy find out the problem, because Z node is associated with dominat pole, break this node may
causes problem

 

[didibabawu]

Re: question about to disconnect the loop of bandgap please

But I think you can break Z too,and you can put a equivalent load at the broken point to see the PM,

 

[tedd]

fundamentally, Z can be break to run ac simulation,
but when Z is the dominant pole, break z may lead to inaccuracy in PM and bandwidth. Additionally, it is hard to determine "equvalent" load.

 

[didibabawu]

Re: question about to disconnect the loop of bandgap please

I think you can get the dc point of the three pmos, and then the dc point can be used to get the equivalent load.

 

[edajason]

Re: question about to disconnect the loop of bandgap please

When breaking the loop, you usually add a large L and a large C (GH/GF) to form a LP filter. So it's connected in DC and disconnected in AC. In this case, it does not hurt to break Z.

fundamentally, Z can be break to run ac simulation,
but when Z is the dominant pole, break z may lead to inaccuracy in PM and bandwidth. Additionally, it is hard to determine "equvalent" load.

 

[tedd]

you gays can refer to MiddleBrook's paper for the problem. In my design, Z is as dominant pole and is connected to a 4pf compensation capacitor ( not show in the attachment), when break this node, where the compensation capacitor can be loacted?? the opamp output side? or the PMOS gate input side?? when you put it at the opamp output side, the PMOS will introdcue difference when comparing with close loop condition.