Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question about the Vctrl of the VCO for PLL

Status
Not open for further replies.

Gstar

Newbie level 3
Joined
Mar 23, 2007
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,298
For PLL, the Vctrl of the VCO will rise from 0V. Does the Vctrl of Voltage controlled delay line rise from 0V too? Or it depends on the structure of the charge pump?
 

Re: DLL Vctrl question

It depends on the structure of VCDL in Analog DLL.
also the structure of VCO in PLL.
 

DLL Vctrl question

Did you mean the initial condition?
Generally I start simulation from 0V...
 

Re: DLL Vctrl question

AMS2007 said:
It depends on the structure of VCDL in Analog DLL.
also the structure of VCO in PLL.

If the VCDL in DLL is single ended inverter-based delay line, and the VCO in PLL is also single ended inverter-based ring oscillator, what will the Vctrl behave for each case? Will it start from 0V? Or start from about half of the supply voltage?

Added after 3 minutes:

DZC said:
Did you mean the initial condition?
Generally I start simulation from 0V...

Yeah, I mean if start fimulation form 0s, what will Vctrl behave?
Will the simulation results be different when the other circuits (not in the DLL loop) are changed?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top