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[SOLVED] Question about the IC compiler

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Fengwei

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Sorry, I am new.
I used a hard macro (SRAM) in my design.
In fact, there are 4 Metal layers in SRAM (total 5 Metal layers).
When I use `route_zrt_auto`, there are a lot of nets in Metal 4 covering the SRAM.
It should be a shot circuit.
Is there a command which can avoid the layout over the hard macro?
 
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Fengwei

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Who can tell me how to solve the "open" error in LVS verification by icc_shell? VDD is open. Or sometimes, VSS is open even though I execute "derive_pg_connection -power_net VDD -power_pin VDD -ground_net VSS".
Who can give me some suggestions?
Thank you in advance.
 

ramkka

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Use route_guide, and please check if there is physical connectivity for VSS and VDD of std cells.
 

Fengwei

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Thanks.
After I use Calibre to verify LVS and DRC, there is no error now.
 

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