question about the design of inverter

[sapphire]

I want to use an inverter as an sense amplifier. In order to have larger gain, I want to work the NMOS and PMOS in subthreshold region. But I don't want to lower the vdd voltage, since it would affect the output range directly.

My question is how can I achieve this while still not changing vdd level? Thanks!

 

[erikl]

An inverter is a digital type of circuit (both gates connected). Subthreshold operation is not a question of supply voltage. It depends on GS-overvoltage Vov=Vgs-Vth. This would mean a difficult bias voltage supply for both gate inputs, a high gain (as you state correctly), but also a very high output impedance, which in most cases can't be matched by the load, hence isn't useful then. So normally a current source load, a triode load, a source follower or a cascode stage is needed, and then it's not an inverter any more, but a single-stage amplifier.

 

[oermens]

see https://books.google.ca/books?id=Qz...X&oi=book_result&resnum=1&ct=result#PPT290,M1

 

[sapphire]

To erikl:

Consider a simple inverter, if Vdd<=Vth+|Vtp|, then both NMOS and PMOS is working in subthreshold when the inverter is in transition. Therefore, we got higher gain (usually 2x or more) than above-threshold region, since in subthreshold the MOS is working like a BJT. Thermal voltage is much smaller than overdrive voltage. But if Vdd is lowered, the output range is also lowered, which is not good.

 

[erikl]

Right, sapphire,
I forgot this possibility. Anyway, you can't get much more gain than about 10, and this at a VDD of about 150mV, cf. p. 16-4, Fig. 16.2b of the E. Vittoz "Weak inversion ..." paper, referenced by oermens (above).

This IMHO only makes sense, if you use such an inverter within a sub_threshold CMOS Standard Cell Library, s. e.g. Eric A. Vittoz and Joyce Kwong "Digital Logic", Chapter 6 of Alice Wang et. al. "Sub-Threshold Design for Ultra Low-Power Systems", Springer Science+Business Media, LLC, NY 2006 .

 

[sapphire]

erikl, at Vdd=150mV, the gain of inverter is about -2.3. As Vdd approaches 2-3 times thermal voltage, the gain is approaching -1. At such a low supply voltage, we can express its gain as -1/n*(exp(Vdd/2Vt) - 1), n is about 1.5, quoted from Rabaey's digital book.

But this equation is only valid for very low supply voltage. As Vdd is a little less than Vtn+|Vtp|, we need to account for DIBL effect, which affects the threshold voltage. So things become more complicated.

Anyway, I got simulated gain of inverter about -500 by using cascode structure and 3.3V mosfet. Vdd is 1V. However, I want to achieve 60 dB.

 

[erikl]

...
Anyway, I got simulated gain of inverter about -500 by using cascode structure and 3.3V mosfet. Vdd is 1V. However, I want to achieve 60 dB.

54dB gain in one stage isn't bad at all! But - as I pointed out above - it isn't a simple inverter any more. ;-)

 

[sapphire]

yeah, it's not a simple inverter. Thanks for your replies.

...
Anyway, I got simulated gain of inverter about -500 by using cascode structure and 3.3V mosfet. Vdd is 1V. However, I want to achieve 60 dB.

54dB gain in one stage isn't bad at all! But - as I pointed out above - it isn't a simple inverter any more. ;-)