ckcson
Newbie level 3
Dear All:
I have an important question about synthesize the inverter chain by using the
Synopsys Design Compiler.
I want to make a odd-number inverter chain to build a digital oscillator.
But the Design Compiler will optimize my design.
What can I do ?
I have try to use the "dont_munch" description , but it still can't fit my idea.
these are my verilog code:
module ring_osc(enable,out1,out2,out3,out4,fout);
input enable;
output fout;
output out1; //synopsys dont_munch "out1"
output out2; //synopsys dont_munch "out2"
output out3; //synopsys dont_munch "out3"
output out4; //synopsys dont_munch "out4"
nand (out1,enable,fout);
not (out2,out1);
not (out3,out2);
not (out4,out3);
not (fout,out4);
endmodule
Thanks a lot for your suggestion.
I have an important question about synthesize the inverter chain by using the
Synopsys Design Compiler.
I want to make a odd-number inverter chain to build a digital oscillator.
But the Design Compiler will optimize my design.
What can I do ?
I have try to use the "dont_munch" description , but it still can't fit my idea.
these are my verilog code:
module ring_osc(enable,out1,out2,out3,out4,fout);
input enable;
output fout;
output out1; //synopsys dont_munch "out1"
output out2; //synopsys dont_munch "out2"
output out3; //synopsys dont_munch "out3"
output out4; //synopsys dont_munch "out4"
nand (out1,enable,fout);
not (out2,out1);
not (out3,out2);
not (out4,out3);
not (fout,out4);
endmodule
Thanks a lot for your suggestion.