I have two circuit expression of signal mux : the first one is a combination circuit and the second one is a sequential circuit.
Which expression is more effective?
Can the sequential circuit miss the transition period of signals?
Code:
invertvsync <= not(sysvsync) when inversevs = '1' else sysvsync;
Code:
process ( refclk )
begin
if (rising_edge(refclk)) then
if (inversevs = ‘1’ ) then
invertvsync <= not(sysvsync);
else
invertvsync <= sysvsync;
end if;
end if;
end process;
Both the multiplexers you describe are identical, except that the 2nd one is followed by a flip-flop (the 'data' input of the flip-flop has the same multiplexer as the 1st).
So, from a multiplexer point of view they are the same (both have the same 'effectiveness'). Clocking it in makes the signal stable from clock-to-clock period. The clocked process will only 'remember' the state at the rising edge of the clock. All changes that occur before that will not appear at the output (nor will changes until the next clock).