iamczx
Member level 3
a question about sdf
when I read the sdf file in dc following the steps:
read_verilog
current_design
create_clock
set_propagated_clock
set_input_delay
set_output_delay
report_timing
..
but the dc told:
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282
)
Information: Reading 'maximum' values for 'maximum delay analysis'. (SDFN-16)
Warning: There is no 'combinational' timing arc between pins
'clk__TOP_I1/A' and 'clk__TOP_I1/Y'. (OPT-815)
Warning: Cell delay could not be annotated between pin 'clk__TOP_I1/A',
and pin 'clk__TOP_I1/Y' for the design 'dac'. (SDFN-6)
。。。
。。
It seems that all the constraints in sdf were ignored.
Any can get some advice?
Thanks in advance.
when I read the sdf file in dc following the steps:
read_verilog
current_design
create_clock
set_propagated_clock
set_input_delay
set_output_delay
report_timing
..
but the dc told:
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282
)
Information: Reading 'maximum' values for 'maximum delay analysis'. (SDFN-16)
Warning: There is no 'combinational' timing arc between pins
'clk__TOP_I1/A' and 'clk__TOP_I1/Y'. (OPT-815)
Warning: Cell delay could not be annotated between pin 'clk__TOP_I1/A',
and pin 'clk__TOP_I1/Y' for the design 'dac'. (SDFN-6)
。。。
。。
It seems that all the constraints in sdf were ignored.
Any can get some advice?
Thanks in advance.