Question about sdf file in DC

[iamczx]

a question about sdf

when I read the sdf file in dc following the steps:
read_verilog
current_design
create_clock
set_propagated_clock
set_input_delay
set_output_delay
report_timing
..
but the dc told:
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282
)
Information: Reading 'maximum' values for 'maximum delay analysis'. (SDFN-16)
Warning: There is no 'combinational' timing arc between pins
'clk__TOP_I1/A' and 'clk__TOP_I1/Y'. (OPT-815)
Warning: Cell delay could not be annotated between pin 'clk__TOP_I1/A',
and pin 'clk__TOP_I1/Y' for the design 'dac'. (SDFN-6)
。。。
。。

It seems that all the constraints in sdf were ignored.
Any can get some advice?
Thanks in advance.

 

[omid219]

a question about sdf

I think the sdf has been generated from other tools (cadence for example) and you have sdf version mismatch occurs. To change the sdf to lower version do the following steps:

1- read your lib
2- read_verilog
3- read_sdf
4- write_sdf -ver 1.0 -context verilog new_sdf_file_name.sdf

Now, you try to annotate this new sdf and it works.

 

[iamczx]

Re: a question about sdf

I think the sdf has been generated from other tools (cadence for example) and you have sdf version mismatch occurs. To change the sdf to lower version do the following steps:

1- read your lib
2- read_verilog
3- read_sdf
4- write_sdf -ver 1.0 -context verilog new_sdf_file_name.sdf

Now, you try to annotate this new sdf and it works.

though there was no warning after re_write the sdf to ver 1.0.
the result is still wrong. I think the rewrite operate just suppress
the warning

 

[omid219]

Re: a question about sdf

No, it does'nt suppress the warning. when you don't get any warning it means that sdf has been annotated successfully. It think one more thing is wrong.
The only thing that I've faced myself, is the input delay. I applied the input values in my test bench with a for example 20 ns delay, then the functionality was Ok!