peen1
Member level 2
Scan insertion question
Hi Guys,
I have a multi million gate design in which all the paths are multi cycles paths. We use clock enables to run different sections of the design at different rates. I have heard that I would have to use a different scan style (cannot use multiplexed_flip_flop) I was told that the clock enable going into the flop would also have to be muxed. Is that true? If so why?
Also I have not been able to find a good doc on scan insertion and DFT. The Advanced chip synthesis (bhatnagar) does not give alot of info.
When I used ambit I did not have to create new ports..the tool used to do it automatically. Can this be done using synopsys?
for ambit I had this
set_global dft_scan_path_connect tieback
set_global dft_scan_avoid_control_buffering true
set_global dft_enable_combinational_loop_check true
set_global dft_enable_race_condition_check true
set_scan_style muxscan
set_scan_mode scan_en 1
Thanks
Hi Guys,
I have a multi million gate design in which all the paths are multi cycles paths. We use clock enables to run different sections of the design at different rates. I have heard that I would have to use a different scan style (cannot use multiplexed_flip_flop) I was told that the clock enable going into the flop would also have to be muxed. Is that true? If so why?
Also I have not been able to find a good doc on scan insertion and DFT. The Advanced chip synthesis (bhatnagar) does not give alot of info.
When I used ambit I did not have to create new ports..the tool used to do it automatically. Can this be done using synopsys?
for ambit I had this
set_global dft_scan_path_connect tieback
set_global dft_scan_avoid_control_buffering true
set_global dft_enable_combinational_loop_check true
set_global dft_enable_race_condition_check true
set_scan_style muxscan
set_scan_mode scan_en 1
Thanks