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Question about scan insertion and DFT

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peen1

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Scan insertion question

Hi Guys,

I have a multi million gate design in which all the paths are multi cycles paths. We use clock enables to run different sections of the design at different rates. I have heard that I would have to use a different scan style (cannot use multiplexed_flip_flop) I was told that the clock enable going into the flop would also have to be muxed. Is that true? If so why?

Also I have not been able to find a good doc on scan insertion and DFT. The Advanced chip synthesis (bhatnagar) does not give alot of info.

When I used ambit I did not have to create new ports..the tool used to do it automatically. Can this be done using synopsys?

for ambit I had this

set_global dft_scan_path_connect tieback
set_global dft_scan_avoid_control_buffering true
set_global dft_enable_combinational_loop_check true
set_global dft_enable_race_condition_check true
set_scan_style muxscan
set_scan_mode scan_en 1


Thanks
 

eda_wiz

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Re: Scan insertion question

HI ,
If you are using gated clock cell for clock gating..... you can add an OR gate in the circuit , so that ENable will be always On while testing.. I guess No need to change the scancell in this case...it saves you power also.

for eg the TSMC 130nm gated clock cell with TEST ENABLE for DFT looks likes this figure
 

kctang

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Re: Scan insertion question

A little bit more info.

If your design have internal gated clocks and you are using scan test methodology, you have to disable clock gating logic during scan test. It's because your internal clock gating control will stop portion of your scan segment from shifting or capture.

Ambit can insert scan chain but cannot tell there are scan structure violations (or even estimate your fault coverage). My preference is to use Synopsys' DFT Compiler.
 

haosg

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Re: Scan insertion question

in dftc of synopsys, dft is also simple,

create_port
set_dft_signal scan_in -port .
or set_signal_type,
or set_scan_signal,
 

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