First of all VHDL is not a programming language, so don't try writing SW programs with VHDL.
VHDL is a hardware description language. So think of what the hardware that is required to do what you want. Your drawing doesn't show how the HW would function. You would need a multiplexer on the input of each counter so you can load different array addresses into the counters. The mux for counter 1 will require a select that is also used as the array address select but appended with 0 and counter 2 will require another address select that is appended with 1 to form the array address. The line between counters doesn't seem to make sense. Interactions between counters can be reduce to one clock if there are independent address generators for each counter and an arbiter between counters accesses. Or use a dual port memory and you can have both counters access different addresses as the same time. I'll let you figure out the reset.
Oh, yeah. Get rid of the variables, you can uses them after you can code everything without them. As a HW guy I've never used variables except in very specific cases where it improves the readability of the code. SW types always want to use variables in VHDL to excess, much to their detriment.
regards